? semiconductor components industries, llc, 2015 january, 2015 ? rev. 8 1 publication order number: mc74ac74/d mc74ac74, mc74act74 dual d-type positive edge-triggered flip-flop the mc74ac74/74act74 is a dual d?type flip?flop with asynchronous clear and set i nputs and complementary (q,q ) outputs. information at the input is transferred to the outputs on the positive edge of the clock pulse. clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. after the clock pulse input threshold voltage has been passed, the data input is locked out and information present will not be transferred to the outputs until the next rising edge of the clock pulse input. asynchronous inputs: low input to s d (set) sets q to high level low input to c d (clear) sets q to low level clear and set are independent of clock simultaneous low on c d and s d makes both q and q high features ? outputs source/sink 24 ma ? act74 has ttl compatible inputs ? these are pb?free devices cp 1 c d 2 cp 2 13 14 12 11 10 9 8 2 1 34567 v cc c d1 d 1 cp 1 s d1 q 1 q 1 c d2 d 2 cp 2 s d2 q 2 q 2 c d 1 s d 1 q 1 d 1 s d 2 q 2 q 2 d 2 gnd q 1 figure 1. pinout: 14?lead packages conductors (top view) pin assignment pin function d 1 , d 2 data inputs cp 1 , cp 2 clock pulse inputs c d1 , c d2 direct clear inputs s d1 , s d2 direct set inputs q 1 , q 1 , q 2 , q 2 outputs see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information www. onsemi.com marking diagrams xxx = ac or act a = assembly location wl or l = wafer lot y = year ww or w = work week g or = pb?free package tssop?14 dt suffix case 948g xxx 74 alyw 1 14 soic?14 d suffix case 751a 1 14 1 14 xxx74g awlyww 1 14 (note: microdot may be in either location)
mc74ac74, mc74act74 www. onsemi.com 2 truth table (each half) inputs outputs s d c d cp d q q l h x x h l h l x x l h l l x x h h h h h h l h h l l h h h l x q 0 q 0 note: h = high voltage level l = low voltage level x = immaterial; = low-to-high clock transition q 0 (q 0 ) = previous q(q ) before low-to-high transition of clock figure 2. logic symbol s d1 q 1 cp 1 q 1 c d1 s d2 q 2 d 2 cp 2 q 2 cd 2 d 1 s d d cp c d q q figure 3. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
mc74ac74, mc74act74 www. onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 v i v cc 0.5 v v o dc output voltage (note 1) 0.5 v o v cc 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i o dc output sink/source current 50 ma i cc dc supply current per output pin 50 ma i gnd dc ground current per output pin 50 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance (note 2) soic tssop 125 170 c/w p d power dissipation in still air at 85 c soic tssop 125 170 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 > 1000 v i latch?up latch?up performance above v cc and below gnd at 85 c (note 6) 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. i o absolute maximum rating must be observed. 2. the package thermal impedance is calculated in accordance with jesd51?7. 3. tested to eia/jesd22?a114?a. 4. tested to eia/jesd22?a115?a. 5. tested to jesd22?c101?a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc supply voltage ac 2.0 5.0 6.0 v act 4.5 5.0 5.5 v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v t r , t f input rise and fall time (note ) ac devices except schmitt inputs v cc @ 3.0 v ? 150 ? v cc @ 4.5 v ? 40 ? ns/v v cc @ 5.5 v ? 25 ? t r , t f input rise and fall time (note ) act devices except schmitt inputs v cc @ 4.5 v ? 10 ? ns/v v cc @ 5.5 v ? 8.0 ? t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac74, mc74act74 www. onsemi.com 4 dc characteristics symbol parameter v cc (v) 74ac 74ac unit conditions t a = +25 c t a = ?40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 3.0 1.5 2.1 2.1 v out = 0.1 v 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 1.5 0.9 0.9 v out = 0.1 v 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 2.99 2.9 2.9 i out = ?50 a 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v *v in = v il or v ih 3.0 ? 2.56 2.46 ?12 ma 4.5 ? 3.86 3.76 i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level output voltage 3.0 0.002 0.1 0.1 i out = 50 a 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v *v in = v il or v ih 3.0 ? 0.36 0.44 12 ma 4.5 ? 0.36 0.44 i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 4.0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc . ac characteristics symbol parameter v cc * (v) 74ac 74ac unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf min typ max min max f max maximum clock frequency 3.3 100 125 ? 95 ? mhz 3?3 5.0 140 160 ? 125 ? t plh propagation delay c dn or s dn to q n or q n 3.3 5.0 8.0 12.5 4.0 13.0 ns 3?6 5.0 3.5 6.0 9.0 3.0 10.0 t phl propagation delay c dn or s dn to q n or q n 3.3 4.0 10.5 12.0 3.5 13.5 ns 3?6 5.0 3.0 8.0 9.5 2.5 10.5 t plh propagation delay c pn to q n or q n 3.3 4.5 8.0 13.5 4.0 16.0 ns 3?6 5.0 3.5 6.0 10.0 3.0 10.5 t phl propagation delay c pn to q n or q n 3.3 3.5 8.0 14.0 3.5 14.5 ns 3?6 5.0 2.5 6.0 10.0 2.5 10.5 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac74, mc74act74 www. onsemi.com 5 ac operating requirements symbol parameter v cc * (v) 74ac 74ac unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf typ guaranteed minimum t s set-up time, high or low 3.3 1.5 4.0 4.5 ns 3?9 d n to cp n 5.0 1.0 3.0 3.0 t h hold time, high or low 3.3 ?2.0 0.5 0.5 ns 3?9 d n to cp n 5.0 ?1.5 0.5 0.5 t w c pn or c dn or s dn 3.3 3.0 5.5 7.0 ns 3?6 pulse width 5.0 2.5 4.5 5.0 t rec recovery time 3.3 ?2.5 0 0 ns 3?9 c dn or s dn to cp 5.0 ?2.0 0 0 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac74, mc74act74 www. onsemi.com 6 dc characteristics symbol parameter v cc (v) 74act 74act unit conditions t a = +25 c t a = ?40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 4.5 1.5 2.0 2.0 v v out = 0.1 v 5.5 1.5 2.0 2.0 or v cc ? 0.1 v v il maximum low level input voltage 4.5 1.5 0.8 0.8 v v out = 0.1 v 5.5 1.5 0.8 0.8 or v cc ? 0.1 v v oh minimum high level output voltage 4.5 4.49 4.4 4.4 v i out = ?50 a 5.5 5.49 5.4 5.4 *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level output voltage 4.5 0.001 0.1 0.1 v i out = 50 a 5.5 0.001 0.1 0.1 *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 4.0 40 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time. ac characteristics symbol parameter v cc * (v) 74act 74act unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf min typ max min max f max maximum clock frequency 5.0 145 210 ? 125 ? mhz 3?3 t plh propagation delay c dn or s dn to q n or q n 5.0 3.0 5.5 9.5 2.5 10.5 ns 3?6 t phl propagation delay c dn or s dn to q n or q n 5.0 3.0 6.0 10.0 3.0 11.5 ns 3?6 t plh propagation delay c pn to q n or q n 5.0 4.0 7.5 11.0 4.0 13.0 ns 3?6 t phl propagation delay c pn to q n or q n 5.0 3.5 6.0 10.0 3.0 11.5 ns 3?6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac74, mc74act74 www. onsemi.com 7 ac operating requirements symbol parameter v cc * (v) 74act 74act unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf typ guaranteed minimum t s set-up time, high or low 5.0 1.0 3.0 3.5 ns 3?9 d n to cp n t h hold time, high or low 5.0 ?0.5 1.0 1.0 ns 3?9 d n to cp n t w c pn or c dn or s dn 5.0 3.0 5.0 6.0 ns 3?6 pulse width t rec recovery time 5.0 ?2.5 0 0 ns 3?9 c dn or s dn to cp *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 35 pf v cc = 5.0 v ordering information device package shipping ? mc74ac74dg soic?14 (pb?free) 55 units/rail MC74AC74DR2G soic?14 (pb?free) 2500/tape & reel mc74ac74dtr2g tssop?14 (pb?free) 2500/tape & reel mc74act74dg soic?14 (pb?free) 55 units/rail mc74act74dr2g soic?14 (pb?free) 2500/tape & reel mc74act74dtr2g tssop?14 (pb?free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc74ac74, mc74act74 www. onsemi.com 8 package dimensions soic?14 nb case 751a?03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74ac74, mc74act74 www. onsemi.com 9 package dimensions tssop?14 case 948g issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ?u? seating plane 0.10 (0.004) ?t? ??? ??? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ?v? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74ac74, mc74act74 www. onsemi.com 10 p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74ac74/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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